Hugetlb pages are incredibly architecture specific at the Memory Management Unit (MMU) level. For example, every arch has a different way of handling the page table entries. This leads to some tricky rules and restrictions on what can be done with huge pages. The following sections describe the issues surrounding these architecture limitations on a per-architecture basis.
PowerPC
The powerpc architecture makes use of segmentation to reduce the flushing of virtual to physical address translations. Each segment is 256M in size and can contain only one page size. For addresses below 4GB, 256MB is the page size granularity. For 64bit addresses above 4GB, the page size granularity is 1TB.